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The serial adder is a digital circuit in which bits are added a pair at a time. Let A and B be two unsigned numbers to be added to produce Sum = A + B. In this we are using three shift registers which are used to hold A, B and Sum. Now in each […]
Serial Adder using Mealy and Moore FSM in VHDL Read More »
Assuming that we have the design concept that defines the expected behaviour and characteristics of the large circuit: Step1: Partition circuit into smaller blocks and then design each block separately. Step 2: After partitioning, circuitry in each block is defined and chips needed to implement it are chosen. Step 3: After designing the blocks, the
Design Flow for Logic Circuit in VHDL Read More »
Terminology: IDS = current from drain to source OR drain-source current VDS = drain to source voltage L = length of the channel Now for the ideal case, in the saturation region, IDS becomes independent of VDS i.e. in the saturation region channel is pinched off at the drain end and a further increase in VDS
Channel Length Modulation in MOSFET (VLSI Design) Read More »
Latch-up is defined as the generation of a low-impedance path in CMOS chips between the power supply (VDD) and the ground (GND) due to the interaction of parasitic PNP and NPN bipolar junction transistors (BJTs).
Latch Up Problem in CMOS – VLSI Design Read More »
1. VHDL code for half adder using Dataflow modelling: library ieee; use ieee.std_logic_1164.all; entity half_adder is port (a, b: in std_logic; sum, carry_out: out std_logic); end half_adder; architecture dataflow of half_adder is begin sum <= a xor b; carry_out <= a and b; end dataflow; 2. VHDL code for half adder using Structural modelling: library
VHDL code for half adder Read More »