B.Tech RTU ECE | Notes | Previous Year Questions - Buzztech

Serial Adder using Mealy and Moore FSM in VHDL

The serial adder is a digital circuit in which bits are added a pair at a time. Let A and B be two unsigned numbers to be added to produce Sum = A + B. In this we are using three shift registers which are used to hold A, B and Sum. Now in each […]

Serial Adder using Mealy and Moore FSM in VHDL Read More »

Design Flow for Logic Circuit in VHDL

VHDL

Assuming that we have the design concept that defines the expected behaviour and characteristics of the large circuit: Step1: Partition circuit into smaller blocks and then design each block separately. Step 2: After partitioning, circuitry in each block is defined and chips needed to implement it are chosen. Step 3: After designing the blocks, the

Design Flow for Logic Circuit in VHDL Read More »

Channel Length Modulation in MOSFET (VLSI Design)

VLSI Design