Latch Up Problem in CMOS – VLSI Design

Latch-up is defined as the generation of a low-impedance path in CMOS chips between the power supply (VDD) and the ground (GND) due to the interaction of parasitic PNP and NPN bipolar junction transistors (BJTs).

VHDL code for half adder

1. VHDL code for half adder using Dataflow modelling: library ieee; use ieee.std_logic_1164.all; entity half_adder is port (a, b: in std_logic; sum, carry_out: out std_logic); end half_adder; architecture dataflow of half_adder is begin sum <= a xor b; carry_out <= a and b; end dataflow; 2. VHDL code for half adder using Structural modelling: library …

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