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Terminology: IDS = current from drain to source OR drain-source current VDS = drain to source voltage L = length of the channel Now for the ideal case, in the saturation region, IDS becomes independent of VDS i.e. in the saturation region channel is pinched off at the drain end and a further increase in VDS […]
Channel Length Modulation in MOSFET (VLSI Design) Read More »
Latch-up is defined as the generation of a low-impedance path in CMOS chips between the power supply (VDD) and the ground (GND) due to the interaction of parasitic PNP and NPN bipolar junction transistors (BJTs).
Latch Up Problem in CMOS – VLSI Design Read More »
The CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. Thus, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C. If the control signal
CMOS Transmission Gate (Pass Gates) Read More »