1. A place-and-route (or fitter) tool is software used to automatically map or fit synthesized logic to a target PLD’s architecture.
2. The place operation selects and configures specific logic primitives in the PLD’s architecture for each logic primitive in the technology dependent netlist.
3. The route operation determines the path for each connection between two logic primitives and each connection between a logic primitive and a pin of the PLD.
4. Place-and-Route tool inputs => a technology dependent gate-level EDIF netlist and constraint information such as pin assignments for port signals and timing constraints.
5. The place-and-route tool maps the EDIF netlist into the PLD’s architecture.
6. A place-and-route tool generally produces three outputs: a chip report, a configuration file, and a VHDL timing model.
- The Chip Report documents which port signals are assigned to which PLD pins and how much of the PLD’s logic capacity is used.
- The Configuration file (programming file) contains the interconnection and configuration data necessary to program the PLD.
- The VHDL timing model is a file containing a structural-style VHDL program that describes the logic and timing of the synthesized logic mapped to the target PLD. This model includes information detailing the propagation delays of signals through the PLD.
7. The placement phase chooses a location on the target device for each logic block in the technology-mapped netlist.
8. Once a location in the chip is chosen for each logic block in a circuit, the routing phase connects the blocks together by using the wires that exist in the chip.