Synthesis vs Simulation in VHDL

Simulation in VHDL:

  1. It describes the behaviour of the circuit in terms of input signals, the output signals, knowledge of delays.
  2. The behaviour described in terms of occurrences of events and waveforms on signals.
  3. In this mode, design description is compiled and simulated and the results are evaluated.
  4. Simulation process in VHDL is based on discrete event simulation.
  5. Discrete event simulation utilizes a sorted event list structure. Each event is described by the type of event and the time it is to occur.
  6. Timestamp of an event is the time at which this event happens. The event list is ordered according to increasing timestamp value.

Synthesis in VHDL:

  1. Synthesis is a process in which a physical system is constructed from an abstract description using a pre-defined set of basic building blocks (e.g. logic gates, flip-flops, latches, small blocks of memory, LUTs in FPGA).
  2. Synthesis is the process of constructing a gate-level netlist from a model of a circuit described in VHDL.
  3. Synthesis process from VHDL model is based on the process of inference (conclusion) of hardware from the description.
  4. Inference is followed by optimization to reduce the size or increase the speed of the inferred circuit.
  5. In this route, VHDL is used as the specification and synthesis language, but the process of transformation into hardware is more automated.
  6. Synthesis process both increases productivity (through automation) and reduces flexibility (by restricting the choice of technology).

 “SIMULATION AND SYNTHESIS ARE COMPLEMENTARY PROCESSES” 

 “EVERYTHING THAT CAN BE SIMULATED CANNOT BE SYNTHESIZED IN VHDL” 

  • Some VHDL constructs are not synthesizable. Therefore, it is possible to write a VHDL description that can be simulated, but not synthesized.
  • For a design description to be synthesizable, we must use only those constructs that are acceptable to our synthesis tool.
  • A synthesis tool infers the logic it synthesizes from the context in which specific constructs appear in a design description.
  • If the VHDL code is physically meaningless or too far removed from the hardware it attempts to describe, it may not be synthesizable.

Difference between Synthesis and Simulation:

S.No.SimulationSynthesis
1.Simulator uses the sensitivity list to figure out when it needs to run the process.Synthesis tools focus on logic design (FPGA, ASIC) and ignore sensitivity list because there are only three basic types of logic:
- Combinational logic
- Edge sensitive storage (FF(s) and some RAM)
- Level sensitive storage (Latches and some RAM)
2.Simulation can verify the timing of the circuit.Synthesis outputs a netlist.
3.Simulation is used to verify the functionality of the circuit.Synthesis is used for converting VHDL description into a set of primitives (equations as in CPLD) or components (as in FPGA’s) to fit into the target technology.

Leave a Comment

Your email address will not be published. Required fields are marked *