VHDL Modelling Styles: Behavioral, Dataflow, Structural

An architecture can be written in one of three basic coding styles:

(1) Dataflow (2) Behavioral (3) Structural.

The difference between these styles is based on the type of concurrent statements used:

• A dataflow architecture uses only concurrent signal assignment statements.
• A behavioral architecture uses only process statements.
• A structural architecture uses only component instantiation statements.

Instead of writing an architecture exclusively in one of these styles, we can mix two or more, resulting in a mixed style.

(1) Dataflow Style of Modelling:

1. Dataflow style describes a system in terms of how data flows through the system. Data dependencies in the description match those in a typical hardware implementation.
2. A dataflow description directly implies a corresponding gate-level implementation.
3. Dataflow descriptions consist of one or more concurrent signal assignment statements.

E.g. Dataflow style half-adder description.

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
  port (a, b: in std_logic;
    sum, carry_out: out std_logic); 
  end half_adder;

architecture dataflow of half_adder is 
  begin
  sum <= a xor b;
  carry_out <= a and b; 
end dataflow;

• The first assignment statement describes how input data flows from inputs a and b through an XOR function to create sum.
• The second assignment statement describes how input data flows through an AND function to produce carry_out.
• Anytime there is an event on either input, the statements concurrently compute an updated value for each output.
• The concurrent signal assignment statements in this description directly imply a hardware implementation consisting of an XOR gate and an AND gate.

(2) Behavioral Style of Modelling:

1. A behavioral description describes a system’s behavior or function in an algorithmic fashion.
2. Behavioral style is the most abstract style. The description is abstract in the sense that it does not directly imply a particular gate-level implementation.
3. Behavioral style consists of one or more process statements. Each process statement is a single concurrent statement that itself contains one or more sequential statements.
4. Sequential statements are executed sequentially by a simulator, the same as the execution of sequential statements in a conventional programming language.

E.g. Behavioral style half-adder description.

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
  port (a, b: in std_logic;
    sum, carry_out: out std_logic); 
  end half_adder;

architecture behavior of half_adder is 
  begin
    ha: process (a, b)
    begin
      if a = ‘1’ then
        sum <= not b;
        carry_out <= b;
      else
        sum <= b;
        carry_out <= ‘0’; 
      end if;
    end process ha;

end behavior;

• The entity declaration is the same as for the dataflow architecture. However, the architecture body is quite different. This architecture consists of a single process statement.
• The process statement starts with the label ha followed by the keyword process. A label on a process is optional, but is useful to differentiate processes in designs that contain multiple processes.
• Following the keyword process is a list of signals in parentheses, called a sensitivity list. A sensitivity list enumerates exactly which signals cause the process to be executed. Whenever there is an event on a signal in a process’s sensitivity list, the process is executed.
• Between the second begin keyword and the keywords end process is a sequential if statement. This if statement is executed whenever the process executes.

(3) Structural Style of Modelling:

1. In structural style of modelling, an entity is described as a set of interconnected components.
2. The top-level design entity’s architecture describes the interconnection of lower-level design entities. Each lower-level design entity can, in turn, be described as an interconnection of design entities at the next-lower level, and so on.
3. Structural style is most useful and efficient when a complex system is described as an interconnection of moderately complex design entities. This approach allows each design entity to be independently designed and verified before being used in the higher-level description.

E.g. Structural style half-adder description.

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is 					-- Entity declaration for half adder 
  port (a, b: in std_logic;
    sum, carry_out: out std_logic);
end half_adder;

architecture structure of half_adder is 	-- Architecture body for half adder

  component xor_gate					-- xor component declaration
    port (i1, i2: in std_logic; 
      o1: out std_logic);
  end component;

  component and_gate					-- and component declaration
    port (i1, i2: in std_logic;
      o1: out std_logic);
  end component; 

begin
   u1: xor_gate port map (i1 => a, i2 => b, o1 => sum);
   u2: and_gate port map (i1 => a, i2 => b, o1 => carry_out);
-- We can also use Positional Association
--	=> u1: xor_gate port map (a, b, sum); 
--	=> u2: and_gate port map (a, b, carry_out);
end structure;

• The half adder is described as an interconnection of an XOR gate design entity and an AND gate design entity.
• Design entity half_adder describes how the XOR gate and the AND gate are connected to implement a half adder. It is this top-level entity that has a structural style description.
• In VHDL, a component is actually a placeholder for a design entity. A structural design that uses components simply specifies the interconnection of the components.
• When components are used, each must be declared. A component declaration is similar to an entity declaration in that it provides a listing of the component’s name and its ports. Component declarations start with the keyword component.
• A port map tells how a design entity is connected in the enclosing architecture.
• In the statement part of the half-adder architecture are two component instantiation statements. Each one creates an instance (copy) of a design entity. Component instantiation statements require unique labels.

u1: xor_gate port map (a, b, sum);
u2: and_gate port map (a, b, carry_out);

(4) RTL Design:

1. A gate-level logic implementation is sometimes referred to as a register transfer level (RTL) implementation.
2. This level describes the logic in terms of registers and the Boolean equations for the combinational logic between the registers.
3. For a combinational system there are no registers and the RTL logic consists only of combinational logic.