2-to-1 MUX using if-then-else statement in VHDL

A 2-to-1 multiplexer consists of two inputs, one select input and one output. Depends on the select signal, the output is connected to either of the inputs. Since there are two input signals only two ways are possible to connect the inputs to the outputs, so one select is needed to do these operations.

Block Diagram of 2-to-1-MUX - VHDL Program
Fig: Block Diagram of 2-to-1-MUX
Truth Table of 2-to-1-MUX: VHDL Program
Fig: Truth Table of 2-to-1-MUX

VHDL Program for 2-to-1 MUX using if-then-else statement:

library ieee;
use ieee.std_logic_1164.all; 

entity mux2to1 is
  port (w0, w1, s : in std_logic;
     f : out std_logic); 
end mux2to1;

architecture behaviour of mux2to1 is 
  process (w0, w1, s)
    if s = ‘0’ then
      f <= w0;
      f <= w1;
    end if;
  end process;
end behaviour;

1 thought on “2-to-1 MUX using if-then-else statement in VHDL”

  1. Just wanted to ask that when we see it’s logic circuit then when s=0 then output should be b w1 rather than w0 ,Is it possible?

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