Event Driven Simulation in VHDL

1. In an event-driven simulation, time is advanced in non-uniform steps whose sizes depend on when event occurs. 2. It responds to each i/p event by executing a sequence of simulation cycles that determine when and to what values the simulated system’s signals change. 3. Advantages: Eliminates the need for the simulator to evaluate the …

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Simulation Approaches in VHDL

1. Simulation is the process of conducting experiments on a model of a system for the purpose of understanding or verifying the operation of the actual system.  2. REQUIREMENTS OF A VHDL SIMULATOR: A VHDL simulator must provide data structures and algorithms that allow it to efficiently simulate the execution of concurrent statements in a …

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