Serial Adder using Mealy and Moore FSM in VHDL

The serial adder is a digital circuit in which bits are added a pair at a time.

Let A and B be two unsigned numbers to be added to produce Sum = A + B. In this we are using three shift registers which are used to hold A, B and Sum. Now in each clock cycle, a pair of bits is added by the adder FSM and at the end of the cycle, the resulting sum is shifted into the Sum register.

Mealy type FSM for serial adder:

Let G and H denote the states where the carry-in-values are 0 and 1. Output value s depends on both the state and the present value of inputs a and b.

In state G and H:

Input valuation	Output (s)	State
00	0	FSM will remain in same state G
01,10	1	FSM will remain in same state G
11	0	FSM moves to state H
01,10	0	FSM will remain in same state H
11	1	FSM will remain in same state H
00	1	FSM moves to state G

Fig: State Diagram for Mealy type serial adder FSM

A single Flip-Flop is needed to represent the two states. The next state and output equations are:

Y = ab + ay + by

s = a ⊕ b ⊕ y

Fig: State table for the Mealy type serial adder FSM

Fig: State-assigned table for the Mealy type serial adder FSM

Fig: Circuit for Mealy type serial adder FSM

The flip-flop can be cleared by the Reset signal at the start of the addition operation.

Moore type FSM for serial adder:

In a Moore type FSM, output depends only on the present state. Since in both states, G and H, it is possible to produce two different outputs depending on the valuations of the inputs a and b, a Moore type FSM will need more than two states. Therefore we will four states namely: G₀, G₁, H₀ and H₁.

Fig: State Diagram for Moore type serial adder FSM

The next state and output equations are:

Y₁ = a ⊕ b ⊕ y₂

Y₂ = ab + by₂ + by₂

s = y₁

Fig: State table for the Moore type serial adder FSM

Fig: State-assigned table for the Moore type serial adder FSM

Fig: Circuit for Moore type serial adder FSM

The only difference between circuits of Mealy and Moore type FSM for serial adder is that in Moore type FSM circuit, output signal s is passed through an extra flip-flop and thus delayed by one clock cycle with respect to the Mealy type FSM circuit.

Also Read:

Difference between Moore and Mealy FSM

References: Fundamentals of Digital Logic with VHDL Design