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Block Diagrams: From Figure 1, we can see that in Moore’s FSM, Input goes into the combinational next state logic block whose outputs are fed to state register. The outputs of the state register are fed to combinational output logic block which gives us the outputs. Also, the output of state register is also feedback […]
Difference between Moore and Mealy FSM Read More »
A 2-to-1 multiplexer consists of two inputs, one select input and one output. Depends on the select signal, the output is connected to either of the inputs. Since there are two input signals only two ways are possible to connect the inputs to the outputs, so one select is needed to do these operations. VHDL
2-to-1 MUX using if-then-else statement in VHDL Read More »
This decoder takes as its input four bits that represent a binary coded (BCD) value and generates a 7-bit output to drive a seven-segment LED. Each segment is a small LED, which glows when driven by an electrical signal. The segments are labelled from a to g as shown in the figure below: VHDL
BCD to Seven-Segment Decoder Program in VHDL Read More »
1. An SRAM block is a two-dimensional (2D) array of SRAM cells, where each cell can store one bit of information. If we need to store m items with n bits each, we can use an array of m × n SRAM cells. 2. The dimensions of the SRAM array are called its aspect ratio.
SRAM in Digital System Design (VHDL) Read More »
Verification using Simulation: 1. Verification is the process used to demonstrate the correctness of a design. We verify that our design description meets its functional and timing specifications before the target PLD is programmed. 2. Verification using simulation can show the existence of errors in a design, but cannot prove that a design is correct.
Verification using Simulation & Testbench in VHDL Read More »